Interphase Tech CONDOR 4221 Instrukcja Użytkownika Pobierz pdf (Strona 18)

Chapter 1 - Introduction

interrupt handler outputs an interrupt vector number for the non-DMA engine interrupts or requests access to the LBUS

for a DMA engine IACK cycles.

CPU/LBUS Interface

The CPU/LBUS Interface links the CPU core with the LBUS resources. The CPU/LBUS interface converts the CPU

Core bus to the LBUS. The Interface is a one-way interface which allows the CPU to act as a LBUS master. The

interface does not allow other LBUS masters to access the CPU Core.

The CPU/LBUS interface is composed of address latches, data-latching transceivers, and control logic. The

CPU/LBUS Interface performs write-posting and read-latching to maximize the CPU bus and the LBUS performance.

The interface also performs relinquish retries, read-modify-write cycles, IACK cycles to the DMA engine,

back-to-back write-write cycles and back-to-back, write-read cycles.

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Interphase Tech CONDOR 4221 Instrukcja Użytkownika Strona 18